Limits. Symbol. Parameter. Conditions. −40°C. +25°C. +85°C. Units. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. IL. Quiescent Device. VDD = V. Data sheet acquired from Harris Semiconductor. SCHSC – Revised September The CDUB types are supplied in lead hermetic dual-in- line. Order Number CD C National Semiconductor Corporation . This datasheet has been downloaded from: Datasheets for.

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The CD includes diodes to protect it from static discharge, but it can still be damaged if it is not handled carefully. Measure the output voltage of the second inverter and the voltage across the capacitor with the scope. Ids-Vds curves for multiple gate-to-source voltages Vgsfrom which we can observe linear and saturation operation regions.

Fairchild Semiconductor – datasheet pdf

Capture a screen shot. Consider the circuit shown in figure You may find the diagram shown below in figure 13 helpful. Observe the DIO8 pin. Make a pin-level wiring diagram for a transmission gate using a CD For example, consider 22,5,7 ; 1,3, Attach screen shots for different Cd datasheet.


Fairchild Semiconductor

Attach screen shots for different VDD. Groups of pins that are not connected are separated by a semicolon. You can download or view the data sheet here or here.

Quick search Enter search terms or a module, class or function name. For example, consider 22,5,7 ; 1,3, Describe the differences between the screenshots other than that they are inverted. However, we do not have those in the lab.

Estimate Vtn from Ids-Vgs curves. If you only give a logic diagram, show pin numbers between logic elements. Each pair shares a common gate pins 6,3, Attach screen shots for working frequencies, and for too high frequencies such that transitions between 0 and VDD are not complete.

We will now datwsheet to construct another D-latch that will serve as slave latch to form our master-slave D Flip-flop as shown in Figure 8 Click on the Figure to view a full-size picture. During the hold phase of the latch, i.

Output of second inverter. You should see a graph similar to the one shown below in figure 4. You should take a total of three screenshots, one dd4007, corresponding to each inverter output. A low budget way to avoid static discharge is to ground yourself before touching an IC. Build a chain of 3 inverters by connecting your inverters in the order shown in figure 4.


Build a CMOS inverter. Determine the VPP and cd datasheet offset setting required for cd datasheet generator.

Because the output datwsheet the first inverter is now zero, the capacitor will begin to discharge through R1, and the opposite side will be charged. There are many advantages of CMOS, with the cx being zero standby power consumption, at least ideally.

Set the function generator to output a Hz sine wave, 5vpp, 2. Also apply logic High to the D input. It is shown in the dashed box cd datasheet as chip 2 in Figure 7 above. Table Of Contents 8. Output datasheeet datasheet second inverter. Clean up Previous topic 7.