BUT11AF datasheet, BUT11AF pdf, BUT11AF data sheet, datasheet, data sheet, pdf, Fairchild Semiconductor, NPN Silicon Transistor. BUT11AF. GENERAL DESCRIPTION. High-voltage, high-speed glass- passivated npn power transistor in a SOT envelope with electrically. BUT11AF NPN Silicon Transistor. Absolute Maximum Ratings TC=25°C unless otherwise noted. Symbol VCBO Parameter Collector-Base Voltage: BUT11AF.

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August 8 Rev 1. Forward bias safe operating area. Switching times waveforms with inductive load. No liability will be accepted by the publisher for any consequence of its use. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

UNIT – – 1. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. Test circuit resistive load. Typical base-emitter and collector-emitter saturation voltages.


Isc Silicon NPN Power Transistor

Test circuit for VCEOsust. August 2 Rev 1. Application information Where application information is given, it is advisory and does not form part of the specification.

These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Stress above one or more of the limiting values bt11af cause permanent damage to the device. Product specification This data sheet contains final product specifications.

Normalised power derating and second breakdown curves. Extension for repetitive pulse operation. Typical base-emitter saturation voltage. Reproduction in whole or in part is prohibited without the prior written consent of the copyright dztasheet. Region of permissible DC operation.

The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. Publication thereof does not convey nor imply any license under patent or other dayasheet or intellectual property rights.


Switching times waveforms with resistive load. Typical DC current gain. August 7 Rev but11ad. Refer to mounting instructions for F-pack envelopes. August 4 Ptot max and Ptot peak max lines. Oscilloscope display for VCEOsust. Reverse bias safe operating area. Observe the general handling precautions for electrostatic-discharge sensitive devices ESDs to prevent damage to MOS gate oxide.


SOT; The seating plane is electrically isolated from all terminals. Exposure to limiting values for extended periods may affect device reliability. Test circuit inductive load.